HIPS 2016

21st International Workshop on High-Level Parallel Programming Models and Supportive Environments

Held in Conjunction With 30th IEEE International Parallel & Distributed Processing Symposium
May 23-27, 2016
Chicago Hyatt Regency, Chicago, Illinois USA


The 21st HIPS workshop, to be held as a full-day meeting on May 23rd at the IEEE IPDPS 2016 conference in Chicago, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

Topics of Interest

Topics of interest to the HIPS workshop include but are not limited to:


Time Event
8:15 -- 8:30 Opening Remarks

Session 1: Debugging and Optimization

8:30 -- 9:00 Detecting Anomalies in Concurrent Programs based on Dynamic Control Flow Changes
Faheem Ullah, Thomas R. Gross
9:00 -- 9:30 Controlling the Memory Subscription of Distributed Applications with a Task-Based Runtime System
Marc Sergent, David Goudin, Samuel Thibault, Olivier Aumage
9:30 -- 10:00 Reducing Redundant Search in Parallel Graph Mining using Exceptions
Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, Jun Sese
10:00 -- 10:30 Coffee Break

Session 2: Heterogenous Computing

10:30 -- 11:00 Evaluating OpenMP 4.0's Effectiveness as a Heterogeneous Parallel Programming Model
Matt Martineau, Simon McIntosh-Smith, Wayne Gaudin
11:00 -- 11:30 Employing Compression Solutions under OpenACC
Ebad Salehi, Ahmad Lashgar, Amirali Baniasadi
11:30 -- 12:00 CAFe: Coarray Fortran Extensions for Heterogeneous Computing
Craig Rasmussen, Matthew Sottile, Soren Rasmussen, Dan Nagle, William Dumas
12:00 -- 1:30 Lunch

Session 3: Parallel Algorithms and Systems

1:30 -- 2:00 Embedding Concurrent Generators
Peter Mills, Clinton Jeffery
2:00 -- 2:30 The Case for Binary Rewriting at Runtime for Efficient Implementation of High-Level Programming Models in HPC
Josef Weidendorfer, Jens Breitbart
2:30 -- 3:00 PTRAM: A Parallel Topology- and Routing-Aware Mapping Framework for Large-Scale HPC Systems
Seyed Hessamedin Mirsadeghi, Ahmad Afsahi
3:00 -- 3:30 Coffee Break
3:30 -- 4:30 Keynote: On the Origin of the Programming-Models
Tim Mattson
Tim Mattson is a parallel programmer (Ph.D. Chemistry, UCSC, 1985). Tim has been with Intel since 1993 where he has worked with brilliant people on great projects such as: (1) the first TFLOP computer (ASCI Red), (2) the OpenMP API for shared memory programming, (3) the OpenCL programming language for heterogeneous platforms, (4) Intel's first TFLOP chip (the 80 core research chip), and (5) Intel's 48 core, SCC research processor. Currently Tim is working in the Parallel Computing lab. He is (1) the PI for our Big Data science and technology center, and (2) leading a small group studying revolutionary approaches to runtime systems for exascale computers.

Abstract: Programming models multiply seemingly without bound. They emerge from university and corporate research labs at a rate that outstrips anyone's ability to cope. For all this prodigious effort, however, only a remarkably tiny number of these models are actually used to any significant degree.

In this talk, we will explore the emergence of new programming models, the sociology connected to their origins, and the factors that allow certain ones to succeed. We will then consider changes that we see just over the horizon in hardware and ask the question; "are we entering a period where new parallel programming models might actually succeed"?

We will then discuss our work to understand the commonly found species of programing models with ExaScale ambitions. In particular, we expose these programming models to our suite of tests (https://github.com/ParRes/Kernels) to explore the survival of the fittest programming model; one that will hopefully carry us into the era of ExaScale computers.
4:30 -- 5:00 A Comparison of High-Level Programming Choices for Incomplete Sparse Factorization Across Different Architectures
Joshua Dennis Booth, Kyungjoo Kim, Sivasankaran Rajamanickam

Submission & Deadlines

Submissions due (Extended): Jan 22, 2016

Notification of acceptance: Feb 8, 2016

Camera-ready papers due: Feb 26, 2016

Please submit papers through the EDAS conference system. Submission for Paper.

Paper Style

The HIPS paper style is identical to the IPDPS paper style. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references.

Paper Templates


Workshop Co-chairs

Steering Committee

Program Committee


Conference Date Location
20th HIPS 2015 May 25, 2015 Hyderabad, India
19th HIPS 2014 May 19, 2014 Phoenix, AZ, USA
18th HIPS 2013 May 20, 2013 Boston, MA, USA
17th HIPS 2012 May 21, 2012 Shanghai, China
16th HIPS 2011 May 20, 2011 Anchorage, Alaska, USA
15th HIPS 2010 April 19-23, 2010 Atlanta, GA, USA
14th HIPS 2009 May 25, 2009 Rome, Italy
13th HIPS 2008 April 14, 2008 Miami, FL, USA
12th HIPS 2007 March 26, 2007 Long Beach, California, USA
11th HIPS 2006 April 25, 2006 Rhodes Island, Greece
10th HIPS 2005 April 4, 2005 Denver, Colorado, USA
9th HIPS 2004 April 26, 2004 Santa Fe, New Mexico, USA
8th HIPS 2003 April 22, 2003 Nice, France
7th HIPS 2002 April 15, 2002 Fort Lauderdale, FL, USA
6th HIPS 2001 April 23, 2001 San Francisco, CA, USA
5th HIPS 2000 May 1, 2000 Cancun, Mexico
4th HIPS 1999 April 12, 1999 San Juan, Puerto Rico, USA
3rd HIPS 1998 March 30, 1998 Orlando, FL, USA
2nd HIPS 1997 April 1, 1997 Geneva, Switzerland
1st HIPS 1996 April 16, 1996 Honolulu, HI, USA