Programme (Updated
June 19 2011)
(You will see MSPC after clicking the checkbox under ``PLDI'' on the FCRC registration page.)
Call for Papers
Despite the capped growth of the peak CPU speed in CMP, the memory wall problem becomes more serious and complex as more CPU/GPU cores are added, and the bandwidth resource becomes managed by multiple memory controllers and influenced by the constant cache interference among applications. Continuing the previous five successful workshops, MSPC 2011 will provide a forum for publishing and discussing the implications of the changes to both memory performance and correctness on various multi- and many-core systems---from supercomputers to servers to mobile devices---and the related software and hardware innovations. Areas of interest include but are not limited to the following topics:
-
•Analysis of memory systems performance (including power, bandwidth, and latency)
-
•Static and dynamic techniques for understanding and improving memory performance
-
•Memory hierarchy design for chip multiprocessors (CMPs)
-
•Hardware and software techniques for ensuring memory safety and detecting memory-related bugs (e.g., memory leaks, dangling pointers, out-of-bounds memory accesses, invalid C pointer arithmetic)
-
•Hardware and software memory models and their impact on programmability and performance
-
•Data race detection and debugging of programs with (possibly intentional) data races
-
•Managed memory and garbage collection optimizations
-
•Prefetching and compression to improve memory system performance
-
•Memory issues in accelerator-based computing (e.g., GPGPU)
-
•Memory system issues in embedded computers and tiny devices
-
•Impact of new storage class memory technologies (e.g., PCM, MRAM)
-
•Specifications of programming language (and library) shared memory semantics
-
•Power management and the impact on correctness/reliability
Software, hardware, and hybrid approaches are encouraged. In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.
